PCB impedance calculator

How to use the PCB impedance calculator

1. Pick single-ended or differential, and microstrip (outer layer) or stripline (inner layer).
2. Choose a stackup preset, or enter your dielectric thickness, copper and εr from the fab's stackup.
3. To size a trace, enter the target (50 Ω, or 85, 90 or 100 Ω for a pair) and, for a pair, the gap. To check an existing trace, switch to impedance from width.
4. Read the width, the delay per mm, and any notes about the inputs being outside a method's range.

For a stripline, enter the dielectric above and below the trace separately. Most inner layers sit closer to one plane than the other, and treating them as centred overestimates the spacing on one side.

How PCB trace impedance is calculated

A trace and its reference plane form a transmission line with inductance L and capacitance C per unit length. Its characteristic impedance is Z0 = √(L/C) and its delay per unit length is √(LC). A wider trace or a thinner dielectric adds capacitance and lowers Z0; a higher εr adds capacitance too and also slows the signal. Copper thickness matters because the trace's side walls add a little capacitance.

There is no exact formula for a microstrip, because the field is partly in the laminate and partly in air. This calculator uses the most widely validated closed-form fits: Hammerstad and Jensen (1980) for a single microstrip, Kirschning and Jansen (1984) for an edge-coupled pair with Jansen's copper-thickness correction, Wheeler (1978) for stripline, and Cohn's conformal-mapping solution (1955) for stripline pairs. For an offset stripline, the trace's capacitance is split between two virtual centred striplines, one for each plane, and combined in parallel. Differential impedance is twice the odd-mode impedance, and delay is √εeff divided by the speed of light, about 3.34 ps/mm in air.

Worked example 1: 50 Ω on a JLCPCB 4-layer board

The 7628 prepreg is h = 0.2104 mm with εr 4.4, under 0.035 mm of copper. Solving Hammerstad-Jensen for 50 Ω gives w = 0.372 mm (14.7 mil), a width-to-height ratio of 1.77. Part of the field is in air, so the effective εr is 3.19, not 4.4, and the delay is 5.96 ps/mm (151 ps/inch).

Worked example 2: a 90 Ω USB pair on the same stackup

With a 0.127 mm (5 mil) gap, Kirschning-Jansen gives 90 Ω differential at w = 0.278 mm (11 mil). Each trace on its own would be 58.3 Ω, so coupling pulls the pair below 2 × Z0: the odd-mode impedance is 45 Ω and the even-mode impedance 69.4 Ω. The odd mode has more field in the air across the gap, so its effective εr drops to 2.69.

Worked example 3: a 100 Ω pair on an inner layer

On layer 3 of JLCPCB's 6-layer JLC06161H-7628 stackup, the trace has 0.2028 mm of prepreg below it and a 0.4 mm core above, with 0.0152 mm copper. Using the thickness-weighted εr of 4.53 and a 0.15 mm gap, Cohn's offset stripline model gives 100 Ω at w = 0.122 mm (4.81 mil). Stripline is fully embedded, so its delay is 7.1 ps/mm, slower than either microstrip above.

Choosing a PCB stackup for controlled impedance

The dielectric height decides almost everything. On a 2-layer 1.6 mm board the plane is so far away that 50 Ω needs a trace about 2.79 mm (110 mil) wide, wider than most chip pads, and a 100 Ω pair only works closely coupled (0.554 mm (21.8 mil) traces with a 0.2 mm gap), which makes it sensitive to the gap. A 4-layer board with a ground plane on layer 2 puts thin prepreg under the top layer, so controlled-impedance traces come out a few tenths of a millimetre wide. JLCPCB's 7628 stackup gives about 0.372 mm (14.7 mil) for 50 Ω and 0.213 mm (8.38 mil) for a 100 Ω pair at a 0.127 mm gap; the thinner 3313 and 1080 prepregs suit fine BGA breakouts.

On six layers and up, put high-speed pairs on stripline between solid planes for shielding, and keep every controlled net referenced to an unbroken plane from end to end. If the dielectric above and below an inner trace differ in Dk, enter a thickness-weighted average, as the 6-layer preset does.

Differential pair routing guidelines and common mistakes

• Pick the gap first, from your fab's minimum and your breakout, then solve for the width.
• Keep width and gap constant along the pair. Every neck-down at a pad or via changes the impedance.
• Match the two traces' lengths at the end where they diverge, and keep the pair coupled elsewhere.
• Never route a controlled trace across a split or gap in its reference plane; the return current detours.
• Keep same-layer ground pour well back from microstrip, or design it as coplanar on purpose. TI's Ethernet checklist asks for at least 3 trace widths, 5 preferred.
• Use the fab's Dk for the exact prepreg, not a generic 4.5, and the finished copper thickness.
• Stay above the fab's minimum trace and space. JLCPCB lists 3.5 mil (0.089 mm) for impedance-controlled multilayer boards; see the PCB design rules guide for the rest.
• Don't size power traces here. Current sets their width; use the trace width calculator.

How accurate is this impedance calculator?

Closed-form models are fits to field-solver results, accurate inside the ranges they were fitted for. Against the 100 Ω geometries Howard Johnson published from the HyperLynx 2-D field solver, this calculator is within 3.1 % on all 38 stripline pairs, centred and offset (mean 0.85 %), and within 3.7 % on his 4 microstrip pairs with thick 1.5 oz copper. The weak spots are flagged in the result: microstrip pairs whose gap is under about three copper thicknesses read high, and offset striplines read high when one plane is more than twice as far as the other.

The shorter IPC-2141 formula, Z0 = 87/√(εr + 1.41) · ln(5.98h / (0.8w + t)), is fine near w/h = 1 but drifts once traces get wide, as the table shows for the JLCPCB 7628 stackup.

The bigger uncertainty is usually the board, not the formula. Real prepreg thickness and Dk vary from lot to lot and with glass weave, etched traces are trapezoids, and solder mask lowers microstrip impedance. Interface specs allow for this with windows such as 81 to 99 Ω for USB 2.0. Use this calculator to plan and route, then order controlled impedance on the fab's stackup and ask for test coupons.

Do this automatically in ProtoFlow

In the ProtoFlow desktop app the numbers from this page become board rules rather than notes. Open Board Setup, choose the layer count, copper weight and dielectric thickness for your fab's stackup, and the editor draws it to scale. Board Setup recognises pairs named like USB_D+ and USB_D- or TX_P and TX_N; put them in a net class and enter the width and gap you worked out here. The Diff Pair tool then routes both traces together at that width and gap, and the status readout shows the width, gap and length skew in millimetres while you route. If you start from KiCad, importing the board brings its stackup across, including each dielectric's Dk. When you are done, run DRC and export Gerbers, drill files and a JLCPCB BOM and CPL. Download ProtoFlow free for macOS, Windows or Linux.