Most first boards fail for boring reasons: a trace the fab could not etch, a via with no annular ring left, a decoupling capacitor a centimetre from its pin, a ground plane sliced under a fast signal. This guide separates the rules you enter into DRC from the guidelines you apply by hand, gives typical numbers, and shows where each one is enforced.
Last reviewed: 2026-08-18 · By ProtoFlow Engineering Team
Quick answer
PCB design rules come in two layers. Manufacturing rules are your fabricator's hard limits — minimum trace width and spacing (often 0.127 mm / 5 mil at low-cost fabs), minimum via drill and annular ring, copper-to-edge clearance, mask and silk limits — and they belong in your EDA tool's DRC before you place a part. Design guidelines are the engineering habits that make the board work: decoupling capacitors at the IC pins, an unbroken ground plane with continuous return paths, power traces sized for current, short crystal and analog traces, thermal relief on plane pads, sensible via use, and silkscreen that helps assembly. Enter the first layer as rules, apply the second as review, and run DRC to zero before ordering.
| Rule | Typical value / practice | Enforced by |
|---|---|---|
| Min trace width / spacing | 0.127 mm (5 mil) at low-cost fabs; wider is cheaper and safer | DRC (net class / board setup) |
| Min via drill / annular ring | ~0.3 mm drill, ≥0.13 mm ring for standard service | DRC |
| Copper-to-edge clearance | ≥0.3 mm (more if V-scored / panelized) | DRC (board outline clearance) |
| Power trace width | From a trace-width calculator for the current and rise | Net class rules + review |
| Decoupling | 0.1 µF at every IC supply pin, bulk cap per rail, shortest loop to ground | Review (schematic + placement) |
| Ground plane / return path | Unbroken plane under signals; no slots under traces | Review; some tools flag plane splits |
| Thermal relief | Spokes on through-hole pads in planes; direct connect for SMD power | Zone settings + DRC |
| Silkscreen | Designators readable, off pads; pin 1 and polarity marks; board name/version | DRC (silk-over-pad) + review |
| Solder mask | Mask expansion per fab; mask dam between fine pads | DRC |
| Courtyards / spacing | No overlapping courtyards; assembly clearance around tall parts | DRC (courtyard overlap) |
Skip the comparison shopping. Try the free one first and see if it does the job.
Download for DesktopEvery fabricator publishes a capability page: minimum trace width and spacing, minimum drill and via size, minimum annular ring, copper-to-edge clearance, solder-mask and silkscreen limits, and hole-to-copper spacing. Those numbers are the first thing you enter into your EDA tool — in KiCad under board setup and net classes, in ProtoFlow in the board setup dialog — because a design rule that exists from the first trace is checked continuously, and one entered on the last day produces a wall of violations. Typical low-cost service is around 0.127 mm (5 mil) trace/space and 0.3 mm via holes; give yourself margin above the minimums wherever the board has room, because margin is free and yield is not.
DRC checks geometry, not intent. The habits below are what separate a board that passes DRC from a board that works: put a 0.1 µF ceramic at every IC supply pin with the shortest possible loop to ground and a bulk capacitor per rail; keep an unbroken ground plane under every signal and never route a slot under a trace, because the return current follows the trace on the layer below; size power traces with a calculator for the current and the temperature rise you accept; keep crystal, RF, and analog traces short and away from switching regulators; place connectors at the edge and tall parts where the enclosure allows; and route differential pairs as pairs.
Vias are cheap; misplaced vias are not. Keep them out of SMD pads unless the fab supports via-in-pad, give ground vias to every decoupling capacitor, and stitch ground planes together near layer changes so return paths stay continuous. On plane connections, use thermal-relief spokes for through-hole pads so they can actually be soldered, and direct connections for surface-mount power pads where you want the copper to carry current and heat. Check the annular ring after any drill-size change — a smaller drill with the same pad is fine, the other way round is a respin.
Silkscreen is documentation for the person (or machine) building and debugging the board: reference designators readable and not under parts, pin-1 markers on every IC and connector, polarity on diodes and electrolytics, and the board name and version. Keep silk off pads (DRC will flag it) and respect the fab's minimum line width and text height. Solder mask expansion and mask dams between fine-pitch pads come from the fab too — leave them at the fab's defaults unless you have a reason. Finally, courtyards: no overlaps, and extra clearance around anything a pick-and-place head or a hand has to reach.
The practical move is to encode as much of this as your tool allows: net classes for power (wider traces, larger vias), clearance rules from the fab, courtyard-overlap and silk-over-pad checks on, and — in tools that support it — custom rules for differential-pair gap and length matching. Then run DRC to zero errors, read every warning, and do a last human pass over the guidelines DRC cannot see: decoupling loops, return paths, and the 3D view for mechanical collisions.
In ProtoFlow, DRC runs against the fab limits you enter in board setup, the AI placement pass keeps decoupling near pins by default, and the manufacturing export flags rule violations before Gerbers are generated; KiCad enforces the same categories through board setup, net classes, and custom design rules. Either way, the rules are only as good as the numbers you gave them.
| Criteria | Rules entered up front (recommended) | Rules checked at the end |
|---|---|---|
| Trace/space, vias, clearance | Enforced from the first trace. | Wall of violations before ordering. |
| Power net widths | Net classes size them automatically. | Manual review of every power trace. |
| Decoupling / return paths | Placement review + AI-assisted placement. | Often missed; board "works" intermittently. |
| Silk / mask / courtyard | DRC catches overlaps. | Caught by the fab (delay) or not at all. |
Reviewed on: 2026-08-18
The fab-driven ones: minimum trace width and spacing (often 0.127 mm / 5 mil at low-cost fabs), minimum via drill and annular ring, copper-to-edge clearance, mask and silk limits. Plus engineering guidelines: decoupling at pins, unbroken ground plane, sized power traces, thermal relief, clean silkscreen.
Signals: the fab minimum with margin (0.2–0.25 mm is comfortable). Power: use a trace-width calculator for the current and allowed temperature rise, then round up. Ground: pour it as a plane.
As close as the footprint allows — millimetres, not centimetres — with the shortest loop from the capacitor through the pin and back to ground, ideally with its own ground via.
Design rule check: the EDA tool compares your layout against the geometric rules you entered (clearances, widths, drills, courtyards, silk). ProtoFlow and KiCad both run DRC; it only knows the rules you gave it.
On through-hole pads connected to planes, yes — otherwise the plane sinks the heat and the joint will not solder well. On SMD power pads, a direct connection is usually preferable for current and heat.
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Searches for pcb design rules, pcb design guidelines, pcb layout guidelines, pcb design best practices, pcb trace width rules, and pcb design rule check want two layers: the fabricator's manufacturing limits (entered into DRC up front) and the engineering guidelines that make a board work (decoupling, ground planes and return paths, power trace sizing, thermal relief, silkscreen). ProtoFlow and KiCad both enforce the first layer through DRC; the second is review.
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