PCB Design Rules and Guidelines: What to Set, What to Check

Every fabricator publishes a capability page: minimum trace width and spacing, minimum drill and via size, minimum annular ring, copper-to-edge clearance, solder-mask and silkscreen limits, and hole-to-copper spacing. Those numbers are the first thing you enter into your EDA tool — in KiCad under board setup and net classes, in ProtoFlow in the board setup dialog — because a design rule that exists from the first trace is checked continuously, and one entered on the last day produces a wall of violations. Typical low-cost service is around 0.127 mm (5 mil) trace/space and 0.3 mm via holes; give yourself margin above the minimums wherever the board has room, because margin is free and yield is not.

DRC checks geometry, not intent. The habits below are what separate a board that passes DRC from a board that works: put a 0.1 µF ceramic at every IC supply pin with the shortest possible loop to ground and a bulk capacitor per rail; keep an unbroken ground plane under every signal and never route a slot under a trace, because the return current follows the trace on the layer below; size power traces with a calculator for the current and the temperature rise you accept; keep crystal, RF, and analog traces short and away from switching regulators; place connectors at the edge and tall parts where the enclosure allows; and route differential pairs as pairs.

Vias are cheap; misplaced vias are not. Keep them out of SMD pads unless the fab supports via-in-pad, give ground vias to every decoupling capacitor, and stitch ground planes together near layer changes so return paths stay continuous. On plane connections, use thermal-relief spokes for through-hole pads so they can actually be soldered, and direct connections for surface-mount power pads where you want the copper to carry current and heat. Check the annular ring after any drill-size change — a smaller drill with the same pad is fine, the other way round is a respin.

Silkscreen is documentation for the person (or machine) building and debugging the board: reference designators readable and not under parts, pin-1 markers on every IC and connector, polarity on diodes and electrolytics, and the board name and version. Keep silk off pads (DRC will flag it) and respect the fab's minimum line width and text height. Solder mask expansion and mask dams between fine-pitch pads come from the fab too — leave them at the fab's defaults unless you have a reason. Finally, courtyards: no overlaps, and extra clearance around anything a pick-and-place head or a hand has to reach.

The practical move is to encode as much of this as your tool allows: net classes for power (wider traces, larger vias), clearance rules from the fab, courtyard-overlap and silk-over-pad checks on, and — in tools that support it — custom rules for differential-pair gap and length matching. Then run DRC to zero errors, read every warning, and do a last human pass over the guidelines DRC cannot see: decoupling loops, return paths, and the 3D view for mechanical collisions.

In ProtoFlow, DRC runs against the fab limits you enter in board setup, the AI placement pass keeps decoupling near pins by default, and the manufacturing export flags rule violations before Gerbers are generated; KiCad enforces the same categories through board setup, net classes, and custom design rules. Either way, the rules are only as good as the numbers you gave them.