Find how much current a plated via carries, or how many vias a current needs, from the hole size, plating and board thickness. It also gives via resistance, voltage drop, thermal resistance and inductance, in mm or mil.
A through via is as long as the board is thick.
10 °C is the usual conservative choice.
Current per via
1.9 A
0.3 mm via, 25 µm plating, 10 °C rise · IPC-2221 on the barrel
Many prototype fabs plate about 18 µm on average, not 25 µm. At 18 µm this via carries 1.48 A. Use the thinner figure unless you order Class 3 plating.
Conservative for steady DC: thermal studies by Brooks and Adam show vias running cooler than a trace with the same copper. Short pulses can go higher.
A standard 0.3 mm finished-hole via with 25 µm (1 mil) plating carries about 1.9 A for a 10 °C temperature rise, using IPC-2221 on the copper barrel. With the 18 µm plating typical of prototype fabs it is about 1.5 A. For more current, put vias in parallel: 3 A needs 2, 5 A needs 3 and 10 A needs 6 of these vias.
If your fab quotes a drill size, a 0.35 mm drill with 25 µm plating is a 0.30 mm finished hole; the calculator does that subtraction for you. Warnings appear when the aspect ratio or drill size gets hard to manufacture.
A via conducts through the copper plated onto its hole wall. Unrolled, that barrel is a strip as wide as the hole's circumference and as thick as the plating, so its cross-section is
A = π × (d + t) × t
with d the finished hole diameter and t the plating thickness. IPC-2221 has no via-specific formula, so the usual method, and the one used here, treats the barrel as a conductor with that cross-section and applies the IPC-2221 current equation I = k × ΔT0.44 × A0.725, with A in square mils and ΔT the temperature rise in °C. The constant k is 0.048 by default; 0.024, the inner-layer value, gives a cautious answer for vias buried in a hot board. This is exactly the model of the trace width calculator, so a via and a trace with the same copper cross-section get the same rating.
The other outputs use textbook formulas: resistance R = ρL ÷ A with copper at 1.724 × 10-8 Ω·m rising 0.393 % per °C, conduction thermal resistance θ = L ÷ (kCu × A) with kCu = 385 W/(m·K), and inductance L ≈ 0.2 × h × (ln(4h ÷ d) + 1) nH with h and d in mm, the Johnson and Graham estimate.
A = π × (0.3 + 0.025) × 0.025 = 0.0255 mm², which is 39.6 mil². With k = 0.048 and a 10 °C rise, I = 0.048 × 100.44 × 39.60.725 ≈ 1.9 A. That barrel holds the same copper as a 1 oz trace 0.729 mm (28.7 mil) wide.
With 18 µm plating, A = π × 0.218 × 0.018 = 0.0123 mm² (19.1 mil²), so each via carries about 1.12 A at a 10 °C rise. 5 A ÷ 1.12 A = 4.46, which rounds up to 5 vias. The same vias with 25 µm plating would need 4.
Each 0.4 mm via with 25 µm plating carries 2.31 A, so 10 A needs 5. Through a 1.6 mm board at its operating temperature of 35 °C, each via is 0.875 mΩ, and 5 in parallel are 0.175 mΩ: a drop of 1.75 mV and 17.5 mW of heat. Vias are rarely the voltage-drop problem; the traces feeding them usually are.
Current per via for a 10 °C rise (and 20 °C in the last column), IPC-2221 on the barrel, standard constant. Hole sizes are finished holes.
| Finished hole | 18 µm plating | 20 µm plating | 25 µm plating | 25 µm, 20 °C rise |
|---|---|---|---|---|
| 0.15 mm (5.91 mil) | 0.93 A | 1.01 A | 1.21 A | 1.65 A |
| 0.2 mm (7.87 mil) | 1.12 A | 1.22 A | 1.46 A | 1.98 A |
| 0.25 mm (9.84 mil) | 1.30 A | 1.41 A | 1.69 A | 2.29 A |
| 0.3 mm (11.8 mil) | 1.48 A | 1.60 A | 1.90 A | 2.58 A |
| 0.35 mm (13.8 mil) | 1.64 A | 1.78 A | 2.11 A | 2.86 A |
| 0.4 mm (15.7 mil) | 1.80 A | 1.95 A | 2.31 A | 3.13 A |
| 0.5 mm (19.7 mil) | 2.10 A | 2.28 A | 2.69 A | 3.65 A |
| 0.6 mm (23.6 mil) | 2.39 A | 2.58 A | 3.06 A | 4.15 A |
Vias needed in parallel, 25 µm plating, 10 °C rise. With 18 µm plating expect about one more per few vias: 10 A takes 7 × 0.3 mm vias instead of 6.
| Current | 0.2 mm (7.87 mil) | 0.3 mm (11.8 mil) | 0.4 mm (15.7 mil) | 0.5 mm (19.7 mil) | 0.8 mm (31.5 mil) |
|---|---|---|---|---|---|
| 1 A | 1 | 1 | 1 | 1 | 1 |
| 2 A | 2 | 2 | 1 | 1 | 1 |
| 3 A | 3 | 2 | 2 | 2 | 1 |
| 5 A | 4 | 3 | 3 | 2 | 2 |
| 10 A | 7 | 6 | 5 | 4 | 3 |
| 15 A | 11 | 8 | 7 | 6 | 5 |
| 20 A | 14 | 11 | 9 | 8 | 6 |
One through via in a 1.6 mm board, 25 µm plating. Resistance at 20 °C; the aspect ratio uses the drill size.
| Finished hole | Barrel copper | Resistance | Thermal resistance | Inductance | Aspect ratio |
|---|---|---|---|---|---|
| 0.2 mm (7.87 mil) | 0.0177 mm² (27.4 mil²) | 1.56 mΩ | 235 °C/W | 1.4 nH | 6.4 : 1 |
| 0.25 mm (9.84 mil) | 0.0216 mm² (33.5 mil²) | 1.28 mΩ | 192 °C/W | 1.3 nH | 5.3 : 1 |
| 0.3 mm (11.8 mil) | 0.0255 mm² (39.6 mil²) | 1.08 mΩ | 163 °C/W | 1.2 nH | 4.6 : 1 |
| 0.4 mm (15.7 mil) | 0.0334 mm² (51.7 mil²) | 0.826 mΩ | 125 °C/W | 1.2 nH | 3.6 : 1 |
| 0.5 mm (19.7 mil) | 0.0412 mm² (63.9 mil²) | 0.669 mΩ | 101 °C/W | 1.1 nH | 2.9 : 1 |
| 0.6 mm (23.6 mil) | 0.0491 mm² (76.1 mil²) | 0.562 mΩ | 84.7 °C/W | 1.1 nH | 2.5 : 1 |
| 0.8 mm (31.5 mil) | 0.0648 mm² (100 mil²) | 0.426 mΩ | 64.1 °C/W | 0.97 nH | 1.9 : 1 |
| 1 mm (39.4 mil) | 0.0805 mm² (125 mil²) | 0.343 mΩ | 51.6 °C/W | 0.9 nH | 1.5 : 1 |
A 0.3 mm finished hole (0.35 mm drill) with 25 µm plating. The current rating stays at 1.9 A for every thickness; what changes is everything that scales with length.
| Board thickness | Resistance at 35 °C | Thermal resistance | Inductance | Aspect ratio |
|---|---|---|---|---|
| 0.6 mm (23.6 mil) | 0.429 mΩ | 61.1 °C/W | 0.35 nH | 1.7 : 1 |
| 0.8 mm (31.5 mil) | 0.572 mΩ | 81.4 °C/W | 0.51 nH | 2.3 : 1 |
| 1 mm (39.4 mil) | 0.715 mΩ | 102 °C/W | 0.69 nH | 2.9 : 1 |
| 1.2 mm (47.2 mil) | 0.858 mΩ | 122 °C/W | 0.87 nH | 3.4 : 1 |
| 1.6 mm (63 mil) | 1.14 mΩ | 163 °C/W | 1.2 nH | 4.6 : 1 |
| 2 mm (78.7 mil) | 1.43 mΩ | 204 °C/W | 1.7 nH | 5.7 : 1 |
| 2.4 mm (94.5 mil) | 1.72 mΩ | 244 °C/W | 2.1 nH | 6.9 : 1 |
The common guideline, from Armstrong and quoted in Altium's documentation, is to stitch ground at no more than λ/20 of the highest significant frequency, and never wider than λ/10. Inside FR-4 (Dk 4.3) the wavelength is c ÷ (f × √Dk), about half the free-space value.
| Frequency | Wavelength in FR-4 | λ/20 pitch | λ/10 limit | Typical source |
|---|---|---|---|---|
| 100 MHz | 1450 mm | 72.3 mm (2850 mil) | 145 mm | Clock harmonics on slow digital boards |
| 500 MHz | 289 mm | 14.5 mm (569 mil) | 28.9 mm | Fast logic edges and memory buses |
| 1 GHz | 145 mm | 7.23 mm (285 mil) | 14.5 mm | The default to assume when you do not know |
| 2.4 GHz | 60.2 mm | 3.01 mm (119 mil) | 6.02 mm | Wi-Fi, Bluetooth, 802.15.4 |
| 5.8 GHz | 24.9 mm | 1.25 mm (49.1 mil) | 2.49 mm | 5 GHz Wi-Fi |
| 10 GHz | 14.5 mm | 0.723 mm (28.5 mil) | 1.45 mm | Microwave and multi-gigabit serial links |
Through vias in a 1.6 mm board, 25 µm plating and a 10 °C rise unless stated. Drop and loss are for the whole group of vias at the scenario current.
| Scenario | Via | Vias needed | Drop and loss |
|---|---|---|---|
| USB-C 5 V at 3 A, VBUS changing layers One 0.3 mm via is just short of 3 A, so use two and place them side by side across the trace. | 0.3 mm, 25 µm, 10 °C rise | 2 × 1.9 A = 3.8 A | 1.7 mV, 5.1 mW |
| USB PD 20 V at 5 A (100 W) on a prototype-fab board Sized for 18 µm average plating rather than 25 µm, which costs one extra via. | 0.3 mm, 18 µm, 10 °C rise | 4 × 1.48 A = 5.9 A | 2 mV, 10 mW |
| 12 V LED strip feed at 2 A One via is almost, but not quite, enough. | 0.3 mm, 25 µm, 10 °C rise | 2 × 1.9 A = 3.8 A | 1.1 mV, 2.3 mW |
| ESP32 3.3 V rail at 0.5 A A small 0.2 mm via has plenty of margin. | 0.2 mm, 25 µm, 10 °C rise | 1 × 1.46 A = 1.46 A | 0.83 mV, 0.41 mW |
| 24 V motor driver, 10 A layer change At a 20 °C rise the same current needs one via fewer. Put the vias in the pour, not in a line. | 0.4 mm, 25 µm, 10 °C rise | 5 × 2.31 A = 11.6 A | 1.8 mV, 18 mW |
| 20 A battery bus with a 20 °C allowance At this current the feeding copper matters more than the vias: use 2 oz copper and pours on both layers. | 0.5 mm, 25 µm, 20 °C rise | 6 × 3.65 A = 21.9 A | 2.4 mV, 49 mW |
Here the vias move heat, not current. The barrel of one 0.3 mm via through a 1.6 mm board has a conduction thermal resistance of about 163 °C/W. A 3 × 3 array in parallel is about 18.1 °C/W and a 4 × 4 array about 10.2 °C/W, before the pad, solder and the spreading copper on the far side are added. Texas Instruments recommends a pitch of about 1.0 mm with 0.3 mm drills as a starting point and notes that smaller vias lose less solder. Connect the vias solidly to an inner ground plane or a bottom-side pour, and tent, plug or fill them if solder loss is a problem.
λ/20 at 2.4 GHz in FR-4 is about 3.01 mm (119 mil), so a via fence along the RF trace and around the antenna keep-out every 3 mm or so is a sound starting point. Copy the module maker's reference layout where one exists.
Applying the IPC-2221 conductor curve to a via barrel is the approximation most via calculators use, because IPC-2221 has no formula of its own for vias. It rates the barrel as if it were a surface trace with the same copper. A real via is surrounded by laminate, which conducts heat better than air does, and it is usually tied to pads, traces and planes that pull heat away from it. That is why Douglas Brooks and Johannes Adam's thermal models show vias running cooler than the traces feeding them, and why the result here is conservative for steady DC.
IPC-2152 is the newer standard built on extensive measurements, but it is chiefly a trace standard; for vias it says the barrel should have at least the cross-sectional area of the conductor coming into it, using several vias if one is not enough. This calculator shows that equivalent width for every via so you can check that rule directly. The choice of constant matters more than the method: the cautious k = 0.024 halves the rating, which is worth using for boards that run hot or sealed.
The thermal resistance covers conduction along an unfilled barrel only, so use it to compare via patterns, not to predict a junction temperature. The inductance formula ignores the return path and is an order-of-magnitude figure. Short current pulses heat a via less than the steady rating suggests. For anything critical, a thermal simulation or a measured prototype is the final word.
In the ProtoFlow desktop app, via sizes live in Board Setup. Each net class has its own via diameter and drill next to its trace width and clearance, so you can give a Power class 0.4 mm vias while signals keep 0.3 mm. The autorouter places the class via whenever a net changes layer, never smaller than the board minimums. In the routing panel, Stitch GND vias adds a ground via beside each signal via when ground has a plane. Choose a fab preset such as JLCPCB or PCBWay and DRC reports any via whose drill, diameter or annular ring falls below that fab's limits. Use this calculator to decide how many vias a high-current path needs, then let the app hold every via on the board to the rules. You can also describe the board in plain English and have the AI draft the schematic and layout to start from. Download ProtoFlow free for macOS, Windows or Linux.
A 0.3 mm finished-hole via with 25 µm (1 mil) plating carries about 1.9 A for a 10 °C rise when IPC-2221 is applied to its barrel, and about 1.5 A with the 18 µm average plating many prototype fabs deliver. A 0.5 mm via carries about 2.7 A.
With 0.3 mm vias, 25 µm plating and a 10 °C rise: 1 for 1 A, 2 for 3 A, 3 for 5 A and 6 for 10 A. With 18 µm plating, 10 A needs 7. Add one more if the board runs warm.
Work out the copper cross-section of the plated barrel, A = π × (d + t) × t, where d is the finished hole and t the plating thickness. Convert it to square mils and use the IPC-2221 conductor formula I = k × ΔT^0.44 × A^0.725, with k = 0.048 (the outer-layer constant most calculators use) or 0.024 for a more cautious answer.
About 1.1 mΩ for a 0.3 mm via with 25 µm plating through a 1.6 mm board at 20 °C, from R = ρL ÷ A. A 0.2 mm via is about 1.6 mΩ. Vias in parallel divide it.
IPC-6012 asks for a minimum average of 20 µm hole-wall copper for Class 2 boards and 25 µm for Class 3. JLCPCB states an average hole plating of 18 µm and PCBWay lists 18 to 25 µm as standard. Unless you order Class 3, size with 18 to 20 µm.
A common rule is no more than λ/20 of the highest significant frequency, measured inside the board where the wavelength is shorter. In FR-4 (Dk about 4.3) that is about 7.2 mm at 1 GHz and 3 mm at 2.4 GHz.
Texas Instruments' QFN layout note recommends thermal vias on a pitch of about 1.0 mm with 0.3 mm drills as a starting point, so a 3 mm pad takes a 3 × 3 array. One 0.3 mm via through a 1.6 mm board has a barrel thermal resistance of about 163 °C/W, so nine of them are about 18 °C/W for the vias alone.
JLCPCB lists a 0.15 mm minimum via hole with a 0.25 mm via diameter for standard 2-layer and multilayer boards, with 0.1 mm holes only for boards up to 1 mm thick. Smaller vias carry less current and raise the aspect ratio, so use them only where the layout needs them.
It is the board thickness divided by the drill diameter. A 0.2 mm drill in a 1.6 mm board is 8:1. PCBWay treats up to 8:1 as standard and rates 10:1 or more with drills under 0.2 mm as harder to make, because the middle of a long, narrow barrel is hard to plate. The calculator warns past 8:1 and again past 10:1.
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