KiCad "Board edge clearance violation": copper too close to the edge
KiCad design rule check (PCB) message: Board edge clearance violation (copper_edge_clearance in kicad-cli reports).
What it means
Copper sits closer to the board outline (Edge.Cuts) than the copper-to-edge clearance allows. When the board is routed out of the panel, copper that close can be cut or exposed. Pull the copper back, or set the clearance to what your fab actually needs.
Common causes
- Tracks or pads routed along the board edge.
- Edge connectors and castellated pads, which are meant to reach the edge.
- A board outline moved after routing.
- Zone fills that run up to the outline.
How to fix it
- Move tracks inward or redraw the zone outline inside the board.
- For edge connectors and castellations, use a custom rule for those footprints rather than lowering the board-wide setting.
Where the setting lives
Board Setup → Design Rules → Constraints → Copper to edge clearance.
Good to know
KiCad 10 also reports this for zone fills, once per zone. A board that was clean in KiCad 8 can show new edge clearance violations after upgrading.
What fabs need
JLCPCB lists 0.2 mm copper-to-edge for a routed outline and 0.4 mm next to a V-cut.
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Checked against KiCad 10's source and documentation. Last reviewed 2026-11-07.
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