Universal Jlink Adapter
by Fescron
Universal Jlink Adapter is a test instrument published by Fescron, with public KiCad design files on GitHub. Check the repository terms before reuse. The project summarises itself as “20 pin SWD/JTAG J-Link to 10 pin (0.1" and 0.05") reconfigurable Cortex-M header with power supply and TagConnect compatibility, as well as with a reset button. (Info about about J-Link Commander and Segger RTT is also given.).”
The repository has collected 99 stars and been forked 15 times, with the last commit 9 months ago.
What’s in the repository
- KiCad schematic and PCB layout source files
- Full revision history, so you can see how the board changed between versions
Licence and reuse
The project ships its own license terms rather than a standard SPDX license. Open the license file in the repository and read it before you reuse the files — custom hardware licenses often restrict commercial manufacture.
Opening it in ProtoFlow
Select Edit in ProtoFlow for the available opening options. Download the source and open supported KiCad schematic or board files in the desktop app; check the project version and external libraries.
- 01 Select “Edit in ProtoFlow” for opening options. Download the source and open supported KiCad files in the app. Other EDA formats may need conversion.
- 02 Work in the imported local copy: rename nets, swap parts against live distributor stock, re-route, or strip it back to the sub-circuit you actually need.
- 03 Keep the original licence and credit Fescron if you publish or sell what you build from it.
This page indexes a public repository. The design, the files and the copyright belong to Fescron; ProtoFlow does not host, mirror or verify them. Details are read from GitHub and refreshed periodically — check the repository for the current state of the project.
