How to Review an AI-Generated PCB Layout Before You Order

Every AI layout tool runs some checks of its own, and you should still run a second one. Different checkers use different rule sets and different connectivity engines, and they do not always agree. We found this on our own work: when we rechecked our reference designs in KiCad on 16 October 2026, after they had passed ProtoFlow's own checks, KiCad found 5 errors on one board and 2 open connections on another.

The fix is cheap. Export the design to the tool your fab-facing review happens in, load your fab's rules and run its DRC before you order. If the AI tool cannot export an editable project, that is worth knowing before you depend on it.

Start with ERC on the schematic, then DRC on the board, and read the unconnected items as carefully as the errors. In KiCad, the DRC dialog also has a schematic parity check that lists footprints missing from the board, extra footprints and net mismatches.

Then check the pin mapping the checkers trust blindly. Small parts such as SOT-23 regulators and transistors come in several pinouts under the same package name; open the datasheet and confirm pin 1 and the pin order. Check the polarity marks on diodes, LEDs and polarized capacitors, and the pin 1 side of every connector, including which way it mates.

The classic miss in an AI-drafted board is a part that is present but in the wrong place: the decoupling capacitor exists, but it sits a long way from the supply pin it serves. DRC will not flag it, because it breaks no rule. This pass is done by eye, with each IC's datasheet layout guidance open.

Check track widths against the current each net carries, using an IPC-2152 based trace width calculator, and remember that vias have a current limit too. Look under every fast signal for an unbroken ground return; a slot or split in the plane under a clock or USB pair forces the return current the long way round.

Differential pairs, such as USB data lines, should run together at the impedance their standard asks for, with matched lengths and as few vias as possible. If the tool routed them as two independent nets, reroute them as a pair. Anything the router did not know about, it did not get right: high-current paths, sensitive analog inputs and RF feeds all deserve a look by hand.

Zone fills are computed, and a stored fill can be stale. Refill every zone before the final DRC; in KiCad, tick "Refill all zones before performing DRC". Then look for copper islands with no net, ground pads joined by too few thermal spokes, and pours that come too close to a high-voltage net. A ground pad that looks connected in an old fill and is isolated after a refill is a fault the fab will build exactly as drawn.

1. 01

   Check against your fab's real limits

   Rules

   Minimum track and spacing, minimum drill, annular ring and board-edge clearance, from your fab's capability page, entered as design rules before the last DRC.

2. 02

   Keep silkscreen off pads and readable

   Silkscreen

   Reference designators near their parts, nothing printed over pads, and polarity marks that survive assembly.

3. 03

   Open the Gerbers in a separate viewer

   Gerbers

   Check copper, solder mask, silkscreen and drill layers as the fab will see them, not as your editor draws them.

4. 04

   Check the BOM and placement files

   Assembly

   Every part number orderable and in stock, and the rotation of each part in the placement file correct for your assembler. Polarized parts and ICs are where a wrong rotation costs a board.

ProtoFlow runs ERC, DRC and a built-in JLCPCB design review inside the editor, exports Gerber X2, Excellon drills and BOM and placement files formatted for JLCPCB assembly, and saves the design as a KiCad project. That last part is what makes the independent check easy: open the project in KiCad, load your fab's rules and run passes 1, 4 and 5 there.