What is an R2R DAC?
A digital-to-analog converter built from an R-2R resistor ladder: only two resistor values, R in series and 2R to each bit, divide the reference in binary steps. An 8-bit R2R DAC uses 16 resistors.
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R2R DAC calculator (R-2R ladder)
Output voltage for any code, or the code for a voltage: this R2R DAC calculator works both ways on an R-2R resistor ladder and gives the step size and output resistance. Add resistor tolerance, GPIO pin resistance and a load to see the worst-case mid-scale DNL, whether the DAC stays monotonic, and the tolerance you need.
Solve for
Examples
bits
V
Ω
2R is twice this.
%
Ω
Optional: output resistance of the GPIO or switch driving each 2R leg.
Ω
Optional: whatever the output drives, if not a high-impedance buffer.
Output voltage (ideal)
2.5 V
- Binary (MSB first)
- 1000 0000
- Step size (1 LSB)
- 19.531 mV Vref ÷ 2^8
- Full-scale output (all ones)
- 4.98047 V
- Output resistance
- 10 kΩ equals R
- Worst-case DNL at mid-scale, ±1 % parts
- +2.58 / −2.58 LSB
- Worst-case error at code 128
- +1.28 / −1.28 LSB 25 mV
- Monotonic with any parts in tolerance
- no
- Tolerance for ±½ LSB DNL
- 0.19 %
Voltage-mode ladder: 2R legs switched between Vref and ground, 2R termination at the LSB end, output at the MSB end. DNL is measured against the average step; Vref error and drift are not included.
⚠ With ±1 % resistors a mid-scale step can go negative (DNL below −1 LSB): the output may fall when the code rises.
Output at key codes, 8 bits, Vref = 5 V
| Code | Binary | Ideal output | Worst error at ±1 % |
|---|---|---|---|
| 0 | 0000 0000 | 0 V | +0.000 / +0.000 LSB |
| 1 | 0000 0001 | 19.531 mV | +0.059 / −0.056 LSB |
| 64 | 0100 0000 | 1.25 V | +1.13 / −1.11 LSB |
| 127 | 0111 1111 | 2.4805 V | +1.30 / −1.30 LSB |
| 128 | 1000 0000 | 2.5 V | +1.28 / −1.28 LSB |
| 192 | 1100 0000 | 3.75 V | +1.11 / −1.13 LSB |
| 255 | 1111 1111 | 4.9805 V | +0.056 / −0.059 LSB |
How does the R-2R ladder DAC output voltage calculation work?
Vout = Vref × code ÷ 2^N. An 8-bit ladder with a 5 V reference outputs 2.5 V for code 128, in steps of 5 V ÷ 256 = 19.53 mV, up to 4.9805 V for code 255. The output resistance is R for every code, so a load RL divides the output by (R + RL) ÷ RL. Accuracy depends on resistor matching: with ±1 % parts the mid-scale step can be off by ±2.58 LSB.
The R-2R ladder DAC formula, explained
In the voltage-mode ladder each bit drives a 2R leg to Vref (1) or ground (0), the legs are joined by series resistors R, a 2R terminator goes from the LSB end to ground, and the output is taken at the MSB end (ADI MT-015, Bourns).
Vout = Vref × D ÷ 2^N 1 LSB = Vref ÷ 2^N Rout = R
- Vref
- voltage of a 1 at each leg (the logic high or reference)
- D
- input code, 0 to 2^N − 1
- N
- number of bits (2N resistors)
- RL
- load resistance at the output
The R-2R ladder formula follows from one fact: every node sees 2R toward the LSB end in parallel with its own 2R leg, which is R, so each bit’s contribution is halved at every stage on the way to the output. With a load, Vout,loaded = Vout × RL ÷ (R + RL). Differential nonlinearity at the transition where bit j turns on is measured against the average step of the endpoint line (ADI MT-010):
DNL(j) = (w(j) − Σ w(i<j)) ÷ (Σ w ÷ (2^N − 1)) − 1
where w(i) is the output with only bit i high. The calculator solves the ladder’s node equations, so pin resistance, a load and any combination of resistor errors are exact, and finds the worst case by searching the corners of the tolerance range.
R-2R ladder DAC examples
Example 1: an 8-bit DAC from 5 V microcontroller pins
Code 200 is 1100 1000. Vout = 5 V × 200 ÷ 256 = 3.906 V. The step is 19.53 mV and the highest output, code 255, is 4.9805 V. With R = 10 kΩ the output resistance is 10 kΩ, so the ladder needs a buffer before any real load.
Example 2: what ±1 % resistors do to an 8-bit ladder
At mid-scale (0111 1111 to 1000 0000) the worst-case DNL with ±1 % parts is ±2.58 LSB, so the step can go negative and the DAC is not guaranteed monotonic. With ±0.1 % parts it is ±0.26 LSB. Holding ±½ LSB needs about 0.19 % resistors, which is why ladders above 8 bits use matched thin-film networks or trimming.
Example 3: pin resistance and a load
Driving the 20 kΩ legs from pins with 50 Ω output resistance makes each leg 20.05 kΩ against 10 kΩ series resistors. That alone moves the mid-scale step by −0.21 LSB and raises the output resistance to 10.02 kΩ. A 100 kΩ load then scales every output by 0.909, a 9.1 % gain error.
R2R DAC step size and required tolerance by resolution
1 LSB for 3.3 V and 5 V references, and the resistor tolerance that keeps the worst-case mid-scale DNL within ±½ LSB.
| Bits | Codes | LSB at 3.3 V | LSB at 5 V | Full scale at 5 V | Tolerance for ±½ LSB |
|---|---|---|---|---|---|
| 4 | 16 | 206.2 mV | 312.5 mV | 4.6875 V | 3.1 % |
| 6 | 64 | 51.56 mV | 78.13 mV | 4.9219 V | 0.77 % |
| 8 | 256 | 12.89 mV | 19.53 mV | 4.9805 V | 0.19 % |
| 10 | 1,024 | 3.223 mV | 4.883 mV | 4.9951 V | 0.049 % |
| 12 | 4,096 | 805.7 µV | 1.221 mV | 4.9988 V | 0.012 % |
| 14 | 16,384 | 201.4 µV | 305.2 µV | 4.9997 V | 0.0031 % |
| 16 | 65,536 | 50.35 µV | 76.29 µV | 4.9999 V | 0.00076 % |
Worst-case mid-scale DNL versus resistor tolerance
Every resistor at the worst end of its tolerance, which bounds what a batch of parts can do. Values beyond ±1 LSB mean the DAC can be non-monotonic at mid-scale.
| Bits | ±0.05 % | ±0.1 % | ±0.5 % | ±1 % | ±2 % | ±5 % |
|---|---|---|---|---|---|---|
| 4 | ±0.008 LSB | ±0.016 LSB | ±0.082 LSB | ±0.16 LSB | ±0.33 LSB | ±0.82 LSB |
| 6 | ±0.033 LSB | ±0.065 LSB | ±0.33 LSB | ±0.65 LSB | ±1.30 LSB | ±3.25 LSB |
| 8 | ±0.13 LSB | ±0.26 LSB | ±1.29 LSB | ±2.58 LSB | ±5.15 LSB | ±12.89 LSB |
| 10 | ±0.51 LSB | ±1.03 LSB | ±5.13 LSB | ±10.26 LSB | ±20.53 LSB | ±51.33 LSB |
| 12 | ±2.05 LSB | ±4.10 LSB | ±20.50 LSB | ±40.99 LSB | ±81.98 LSB | ±204.97 LSB |
Building an R-2R DAC that behaves
Matching matters more than absolute value: the output depends only on resistor ratios, so a ladder network whose resistors are made together tracks far better than loose parts of the same tolerance, and the bound above, which lets every resistor wander independently, is pessimistic for them. Making each 2R from two R in series of the same part number also helps. Treat the reference as part of the DAC: when the legs are driven from GPIO pins, the supply rail is the reference and its noise and tolerance appear on the output. Buffer the output with an op amp, since the ladder’s output resistance is R. Expect glitches at major carries, where many bits switch at once and do not all change at the same instant; a small RC after the ladder smooths them at the cost of settling time.
Glossary
- R-2R ladder
- A DAC network of only two resistor values, R in series and 2R to each bit, which divides the reference in binary steps.
- LSB (step size)
- The output change for one code: Vref ÷ 2^N.
- DNL
- Differential nonlinearity: how far one step differs from the average step, in LSB.
- Monotonic
- The output never falls when the code rises. A DAC is non-monotonic if any step has DNL below −1 LSB.
- Major carry
- A code change where many bits flip at once, such as 0111 1111 to 1000 0000 at mid-scale.
- Termination resistor
- The 2R from the LSB end of the ladder to ground that makes every node see R.
Related guides
- Op amp gain calculator: buffer or scale the ladder output.
Frequently asked questions
How does an R2R DAC work?
In a voltage-mode ladder, each bit drives a 2R leg to Vref (1) or ground (0). Every node sees 2R toward the LSB end in parallel with its own 2R leg, which is R, so each bit’s contribution is halved at every stage on the way to the output.
What is the R2R DAC formula for output voltage?
Vout = Vref × code ÷ 2^N for an unloaded voltage-mode ladder. Each bit contributes half as much as the bit above it, so with 8 bits and a 5 V reference, code 128 gives 2.5 V and each step is 19.53 mV.
What is the output resistance of an R-2R ladder?
R, for every code and any number of bits. Looking into any node of a correctly terminated ladder you see 2R in parallel with 2R, so the Thevenin resistance at the output is R (ADI MT-015 notes it is independent of code). A load RL scales the output by RL ÷ (R + RL).
What resistor tolerance does an R-2R DAC need?
The mid-scale step is the most sensitive. For a worst case of ±½ LSB there, with every resistor free to sit anywhere in its tolerance, 6 bits need 0.77 %, 8 bits 0.19 %, 10 bits 0.049 % and 12 bits 0.012 %: roughly halving for each extra bit.
Why does an R-2R DAC never reach the reference voltage?
The top code, all ones, is 2^N − 1, so the highest output is Vref × (2^N − 1) ÷ 2^N, one LSB below Vref: 4.9805 V for 8 bits at 5 V. ADI MT-010 describes the same for every DAC.
Can I drive an R-2R ladder straight from microcontroller pins?
Yes; Microchip AN655 does exactly that with a PIC port. The pin’s output resistance adds to every 2R leg, so the legs are no longer exactly twice the series R and the transfer curve bends; for 1 LSB accuracy at 8 bits AN655 makes the 2R value at least 256 times the pin’s source impedance (under 75 Ω at 5 V on those parts); scale that 2^N rule for other resolutions. The output then follows the supply, so a noisy rail shows up on the DAC output.
What value of R should I use?
High enough that pin or switch resistance is negligible against 2R and the reference can supply the current, low enough that the output settles quickly into stray capacitance. 10 kΩ / 20 kΩ is a common choice. Buffer the output with an op amp unless the load is far above R: even a load of 100 × R costs 0.99 % of gain, 2.5 LSB at 8 bits.
What is the difference between voltage-mode and current-mode R-2R DACs?
In voltage mode (this calculator) the legs switch between Vref and ground and the output is the voltage at the ladder end, with a constant output resistance. In current mode the reference drives the ladder end and the legs steer current into an op amp virtual ground; the switches stay near ground and the reference can be negative or AC, as in multiplying DACs (ADI MT-015).
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Sources
- Analog Devices MT-015, Basic DAC Architectures II: Binary DACs (voltage-mode and current-mode R-2R ladders)
- Analog Devices MT-010, The Importance of Data Converter Static Specifications (DNL, monotonicity)
- Bourns, R/2R Ladder Networks (topology, termination, standard ±2 % tolerance)
- Microchip AN655, D/A Conversion Using PWM and R-2R Ladders
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