Decoupling & bypass capacitors
A digital chip draws its current in sharp spikes, one on every clock edge as thousands of transistors switch at once. Those spikes need to be served instantly, but the regulator is far away in electrical terms. The trace between them has inductance, and inductance resists exactly the fast current changes the chip is demanding. Left unmanaged, the supply dips and bounces right at the chip’s pins.
A decoupling capacitor fixes this by acting as a local reservoir. A small capacitor placed at the chip’s power pin delivers the spike from millimeters away, then quietly recharges from the supply between demands. The usual recipe is a 100 nF ceramic per power pin plus a larger bulk capacitor, 10 µF or more, per chip or board region to handle slower swings.
Placement is most of the value. The same capacitor a few centimeters from the pin sits behind enough trace inductance to be useless at high frequency. That’s why every datasheet’s reference layout shows capacitors crowded against the chip, and why experienced reviewers look at decoupling placement before almost anything else. Mysterious resets and flaky behavior very often start here.
Key points
- Chips draw current in fast spikes. Trace inductance keeps distant supplies from responding in time.
- Decoupling capacitors are local reservoirs that serve the spike and then recharge.
- Standard recipe: 100 nF ceramic at every power pin, plus bulk capacitance per region.
- Placement is critical. Millimeters from the pin, or the capacitor barely works.
Practice
0 of 3 answered · Not startedWrong answers just let you try again, and hints are there if you want them. Answering every question first time, without hints, is what earns mastery.
- 1
Why does placing a decoupling capacitor close to the IC pin matter so much?
- 2
Why are bulk and small ceramic capacitors often used together on one rail?
- 3
Which of these actually improve a decoupling capacitor's effectiveness?
Select every answer that applies.
