| 1. Requirements | Power source, MCU/ICs, interfaces, connectors, size, environment | Can you list every connector and its pinout? |
| 2. Schematic | Capture with real parts (symbol + footprint + orderable MPN) | ERC clean; every power pin has a net |
| 3. Parts | Confirm stock, price, package, footprint vs datasheet | No footprint you have not checked against the land pattern |
| 4. Board setup | Layer count, outline, stackup, fab design rules | Rules entered before the first part is placed |
| 5. Placement | Group by function; decoupling at pins; connectors at edge; keep-outs | Every IC's decoupling within a few mm of its pin |
| 6. Routing | Power wide and first; ground plane; short crystal/RF; then signals | No return-path breaks under critical traces |
| 7. DRC | Run against the fab's real limits | Zero errors; understood warnings |
| 8. Silkscreen + 3D | Reference designators, polarity, pin 1, board name/version | 3D view shows no collisions |
| 9. Outputs | Gerbers, drill, BOM, pick-and-place | Load Gerbers in a viewer before ordering |
| 10. Order + bring-up | Fab (and assembly) → test power rails first | Rails correct before populating/powering everything |