AI Circuit Board Design: From Prompt to Fabricated PCB in 2026

Two years ago, AI in PCB tools meant autocomplete for part values. In 2026 it means something concrete: you describe the board you want, "USB-C powered ESP32-S3 sensor node with a LiPo charger and a Qwiic connector", and the tool drafts a real schematic with symbols, nets, and orderable parts, then helps place and route the physical board. The output is not an image of a circuit; it is an editable design that flows to fabrication.

The honest framing is that AI has become a very fast junior engineer. It knows the standard scaffolding cold: decoupling networks, USB terminations, regulator selection, strapping pins, connector pinouts. It drafts in seconds what takes an evening by hand. What it does not have is judgment about your specific constraints, which is why every good AI board workflow is a loop of AI drafts, human reviews, checks confirm.

Schematic generation is the most mature stage. Modern generators often produce connected drafts that pass ERC for the boards engineers actually build, microcontroller breakouts, power supplies, sensor chains, interface boards, because those designs are heavily patterned. The generator knows an ESP32 wants its EN pin on an RC delay and its strapping pins pulled the right way, because thousands of reference designs agree.

The quality gate is whether the schematic is made of real parts. A draft built from generic symbols still leaves you the real work: finding an orderable regulator, checking its dropout, matching the footprint. Tools that attach actual LCSC, DigiKey, and Mouser part numbers during generation remove that step, and give the layout stage real footprints to work with.

Once the schematic exists, the board has to be placed and routed, and this is where AI assistance has improved fastest. Placement assistants, where a tool offers them, cluster decoupling capacitors against their pins and keep crystals short; autorouters take the bulk of the ratsnest off your hands. Cloud services like Quilter and DeepPCB route uploaded boards as a service, and desktop tools route locally, ProtoFlow ships an auto-router inside its PCB editor, with presets, layer filters, and a completion summary, so the route-inspect-fix loop stays in one tool and your files stay on your machine.

The discipline that makes autorouting work on real boards: route the critical sections yourself first, USB pairs, RF, high-current paths, then let the autorouter fill in the rest, and always run DRC afterward. A DRC-aware router keeps to the rules you set, but the rules have to be right: set your fab house clearances before routing, not after.

ProtoFlow is our product, so here are only results checked outside it, in KiCad. On LG AI Research's public PCBWorld-Bench (October 13, 2026, one attempt per board, every attempt counted), ProtoFlow Studio, our AI agent, running Claude Opus 5.5 (a paid setup) left 98 of 99 small boards clean under KiCad's design-rule check; the one miss was a ProtoFlow file-save bug, and that board was clean once it was fixed. All 30 medium-board attempts were clean.

On IO Rodeo's open-source Rodeostat (October 16, 2026), Studio kept the designer's placement and made all 372 connections with zero KiCad errors and no part moved. From the one-line prompt "make me a garage opener" (September 26, 2026), ProtoFlow's AI designed a 47-part, 2-layer board; a KiCad 8 check of the saved, later compacted board found 0 errors and 0 unconnected items (with 106 warnings).

Those results are evidence for those boards, not a promise for yours. Every AI-drafted board still needs the review described below.

ERC and DRC are not bureaucracy in an AI workflow; they are the contract. ERC catches the generator connecting two outputs or leaving an enable floating. DRC catches the autorouter squeezing past your fab minimums or the placement stage overlapping courtyards. Both checks are instant, and both produce the reviewable list a human needs to sign off a machine-drafted design.

The failure modes AI actually exhibits are predictable: a plausible-but-wrong part variant, a missing pull resistor on an obscure enable pin, thermal relief on a pad that needs solid copper. Every one of those is visible in a five-minute review armed with the checker output. None of them is visible if you skip the review because the board "looks done".

Here is the full chain as it runs today in ProtoFlow, free, on a desktop. One: describe the board in plain English, including power source, interfaces, and any parts you already know you want. Two: review the generated schematic, swap any part you disagree with (the AI imports alternatives from LCSC, DigiKey, or Mouser with datasheets attached), and run ERC, then simulate any block you are unsure of with the built-in SPICE (ngspice). Three: sync to the PCB editor, place the parts yourself, starting with connectors, modules, and decoupling, route the critical nets, and run the auto-router on the rest. Four: run DRC and the built-in JLCPCB design review, fix what they flag, and export Gerbers, drill files, and JLCPCB BOM and placement files, or a KiCad project if you want to finish in KiCad.

For a typical microcontroller board, that chain is an afternoon, with most of it spent on the two review passes, which is exactly where your time should go.

Novel analog design, tight RF layout, and safety-critical work remain human territory. The generator has seen ten thousand buck converters, so it drafts yours well; it has not seen your custom sensor front-end, so it will draft something generic that you must redesign. Impedance-controlled routing and EMC-driven stackup decisions still want an engineer who understands why, not just what.

The practical rule: use AI for everything patterned, boilerplate schematic sections, library work, bulk routing, checklist verification, and spend the recovered hours on the parts of your board that are genuinely yours.