Half Adder Circuit Diagram with Logic Gates

Adding two bits has four cases: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1 and 1 + 1 = 10 in binary. The right-hand digit is the sum and the left-hand digit is the carry.

The sum is 1 when exactly one input is 1. That is the definition of exclusive OR, so U1, an XOR gate, produces Sum = A ⊕ B.

The carry is 1 only when both inputs are 1, which is an AND gate: U2 gives Carry = A · B. Both gates read the same two inputs, so A and B each branch to both gates. The dots mark where each input splits; where the A branch crosses the B wire there is no dot, so they are not connected.

A half adder has no carry input, so on its own it can only add the lowest bits of two numbers. Two half adders and an OR gate make a full adder, and a chain of full adders adds numbers of any width.

• Using an OR gate for the sum. OR gives 1 for 1 + 1, but the sum bit of 1 + 1 is 0.
• Leaving unused inputs floating on the real chips. CMOS inputs must be tied high or low, or they can oscillate and draw extra current.
• Drawing a dot where wires only cross. A dot means a connection; crossing wires without one are separate nets.
• Forgetting decoupling. Each 74HC chip needs a 100 nF capacitor between VCC and GND, close to its pins.