Schematic Capture vs PCB Layout vs Routing: What AI Automates

Newcomers to hardware often treat "PCB design" as one monolithic task. It is not. A board goes through three sequential stages, each with its own inputs, outputs, tools, and ways to go wrong. Conflating them is the single most common reason people misjudge what an AI tool can and cannot do for them.

The three stages are schematic capture, layout (placement), and routing. Capture answers "what are the parts and how are they electrically connected?" Layout answers "where does each part physically sit on the board?" Routing answers "how does copper connect the pins while respecting manufacturing rules?" You cannot meaningfully start the next stage until the previous one is correct.

This sequence also explains the AI landscape. Different vendors attack different stages because they are genuinely different problems. Understanding the boundaries lets you assemble a workflow that uses the right tool at each step instead of waiting for one tool to do everything.

Schematic capture is where you declare intent. You place component symbols (a resistor, an MCU, a USB-C connector) and draw connections between their pins. Each connection belongs to a named net, for example VCC_3V3, GND, or USB_DP. A net is simply a set of pins that are electrically the same node. The schematic is a logical drawing; nothing on it has physical position or size yet.

The critical detail is that every symbol must be paired with a real footprint and the right part. A 0402 resistor and an 0805 resistor are electrically identical on the schematic but occupy different land patterns on the board. Capture is also where you assign actual manufacturer parts, so that a symbol maps to, say, a specific LCSC, DigiKey, or Mouser part number with a known symbol and footprint.

This is the stage where ProtoFlow's AI does the most. You describe a circuit in plain English, and ProtoFlow generates an editable, manufacturable schematic with real parts imported from LCSC, DigiKey, and Mouser, complete with symbols and footprints. It runs ERC to catch electrical mistakes before you ever think about a board outline. The same project then carries on into ProtoFlow's PCB editor for layout and routing, covered below.

Layout, also called placement, is the first physical stage. You import the netlist into a PCB editor and the tool gives you a footprint for every component plus a tangle of thin lines called the ratsnest. Each ratsnest line represents a net connection that still needs copper. Your job is to drag footprints into sensible positions on the board outline.

The artifact here is the board itself, a file like a KiCad .kicad_pcb project, with footprints positioned but copper not yet drawn. The ratsnest is still present, which is the visual cue that routing has not happened. Layout decisions also lock in mechanical constraints such as mounting holes, board dimensions, and keep-out zones.

Pure-AI tools are less dominant here than people expect, because placement is tightly coupled to both routing and human intent. Some tools blend placement with routing in one pass. In ProtoFlow the PCB editor syncs from the schematic, so you arrive at this point with every footprint and net already defined and place by hand with the stackup and 3D view in front of you. KiCad remains the common free desktop home for this stage, and ProtoFlow can export the project there if that is where your team lays out.

Routing converts each ratsnest line into actual copper: traces on signal layers, vias between layers, and copper pours for power and ground planes. Every trace must obey design rules, the physical limits of your fabricator, such as minimum trace width, minimum spacing between copper, and minimum drill size. These rules are enforced by DRC, the design rule check.

Routing is also where signal-integrity intent becomes geometry. A USB or Ethernet pair must be routed as a differential pair with controlled impedance and length matching. Power traces must be wide enough to carry current without excessive voltage drop. Sensitive analog nets must stay away from noisy switching nodes. None of this is captured by the netlist alone; it lives in constraints and in the router's behavior.

Routing is the stage with the most mature pure-AI offerings. Quilter (quilter.ai) and DeepPCB (deeppcb.ai, by InstaDeep) operate on an existing board: you give them placed components and a board outline, and they generate routed, DRC-aware candidates. They export back to formats like KiCad, Altium, or Cadence so you can finish and verify in your own tools. Full editors route too: ProtoFlow's PCB editor has interactive routing and an auto-router with presets, layer filters, and a completion summary that shows what is left to finish by hand.

The cost of a mistake rises sharply with each stage you pass before catching it. Rename a mislabeled net during capture and the fix takes seconds. Catch that same error as a wrong connection after the board is fabricated and you are ordering a new batch.

ERC, the electrical rule check, runs at the schematic level. It flags issues like an output pin driving another output, an unconnected input, or a power net with no source. Fixing an ERC violation means editing a drawing, which is cheap.

DRC runs at the board level and flags physical violations: traces too close together, a trace narrower than the fab allows, a via that collides with a pad. Fixing a DRC violation means rerouting copper, which is more work but still pre-fabrication.

Once you see the three stages clearly, the tool landscape sorts itself out. Different tools reason about different problems: a schematic-capture model reasons about parts and connectivity, while a router reasons about geometry and physics under design rules.

A smart approach keeps every stage and its artifact explicit, whether one tool carries the board or several. One concrete path in ProtoFlow: generate the schematic and netlist with real parts and clear ERC, sync to the PCB editor and place the footprints yourself, route the critical nets by hand and let the auto-router fill in the rest. If your team lays out in KiCad, export the project after capture and place there, and if you want a specialised cloud router, hand the placed board to Quilter or DeepPCB. Either way, run human-supervised DRC and ERC before generating Gerbers.

Each handoff is a clean artifact: a netlist out of capture, a placed board file out of layout, routed copper and then Gerbers out of routing. Because the boundaries are explicit, you can swap any one tool without disrupting the others. If a better AI router appears next year, you change one step.