Key takeaways
- Schematic capture defines components and nets; layout positions footprints; routing draws copper. They are distinct problems, not one continuous task.
- Each stage hands off a specific artifact: capture produces a netlist, layout produces a board with placed footprints, routing produces Gerbers for fabrication.
- Errors are cheapest to fix at capture (rename a net) and most expensive after fab (respin a board). ERC and DRC exist to catch them early.
- No single AI tool reliably nails all three stages. ProtoFlow targets capture; Quilter and DeepPCB target placement and routing.
- A practical 2026 workflow chains stage-specific tools and keeps a human on final DRC/ERC review.
Orientation
Why this distinction matters
Newcomers to hardware often treat "PCB design" as one monolithic task. It is not. A board goes through three sequential stages, each with its own inputs, outputs, tools, and ways to go wrong. Conflating them is the single most common reason people misjudge what an AI tool can and cannot do for them.
The three stages are schematic capture, layout (placement), and routing. Capture answers "what are the parts and how are they electrically connected?" Layout answers "where does each part physically sit on the board?" Routing answers "how does copper connect the pins while respecting manufacturing rules?" You cannot meaningfully start the next stage until the previous one is correct.
Stage 1
Schematic capture
What are the parts, and how are they electrically connected?
Hands off
A netlist
Stage 2
Layout / placement
Where does each part physically sit on the board?
Hands off
A placed .kicad_pcb
Stage 3
Routing
How does copper connect the pins while honoring DRC?
Hands off
Gerbers + drill files
This sequence also explains the AI landscape. Different vendors attack different stages because they are genuinely different problems. Understanding the boundaries lets you assemble a workflow that uses the right tool at each step instead of waiting for one tool to do everything.
Stage 1 · Capture
Schematic capture: define components and nets
Schematic capture is where you declare intent. You place component symbols (a resistor, an MCU, a USB-C connector) and draw connections between their pins. Each connection belongs to a named net, for example VCC_3V3, GND, or USB_DP. A net is simply a set of pins that are electrically the same node. The schematic is a logical drawing; nothing on it has physical position or size yet.
The critical detail is that every symbol must be paired with a real footprint and the right part. A 0402 resistor and an 0805 resistor are electrically identical on the schematic but occupy different land patterns on the board. Capture is also where you assign actual manufacturer parts, so that a symbol maps to, say, a specific LCSC, DigiKey, or Mouser part number with a known symbol and footprint.
This is the stage ProtoFlow automates. You describe a circuit in plain English, and ProtoFlow generates an editable, manufacturable schematic with real parts imported from LCSC, DigiKey, and Mouser, complete with symbols and footprints. It runs ERC to catch electrical mistakes before you ever think about a board outline. ProtoFlow is deliberately scoped to this step. It does not place or route.
Stage 2 · Layout
Layout and placement: position the footprints
Layout, also called placement, is the first physical stage. You import the netlist into a PCB editor and the tool gives you a footprint for every component plus a tangle of thin lines called the ratsnest. Each ratsnest line represents a net connection that still needs copper. Your job is to drag footprints into sensible positions on the board outline.
The artifact here is the board itself, a file like a KiCad .kicad_pcb project, with footprints positioned but copper not yet drawn. The ratsnest is still present, which is the visual cue that routing has not happened. Layout decisions also lock in mechanical constraints such as mounting holes, board dimensions, and keep-out zones.
Pure-AI tools are less dominant here than people expect, because placement is tightly coupled to both routing and human intent. Some tools blend placement with routing in one pass. KiCad remains the common free desktop home for this stage, and ProtoFlow's one-click KiCad export bundle is designed to drop you into exactly this point with parts and nets already defined.
Stage 3 · Routing
Routing: draw copper traces honoring DRC
Routing converts each ratsnest line into actual copper: traces on signal layers, vias between layers, and copper pours for power and ground planes. Every trace must obey design rules, the physical limits of your fabricator, such as minimum trace width, minimum spacing between copper, and minimum drill size. These rules are enforced by DRC, the design rule check.
Routing is also where signal-integrity intent becomes geometry. A USB or Ethernet pair must be routed as a differential pair with controlled impedance and length matching. Power traces must be wide enough to carry current without excessive voltage drop. Sensitive analog nets must stay away from noisy switching nodes. None of this is captured by the netlist alone; it lives in constraints and in the router's behavior.
Cloud AI router
Quilter
Takes placed components plus a board outline and generates routed, DRC-aware candidates, often via reinforcement learning. Exports back to KiCad, Altium, or Cadence.
Cloud AI router
DeepPCB (InstaDeep)
Operates on an existing board: feed it a placement and outline, get routed candidates back in your own CAD format to finish and verify.
Routing is the stage with the most mature pure-AI offerings. Quilter (quilter.ai) and DeepPCB (deeppcb.ai, by InstaDeep) operate on an existing board: you give them placed components and a board outline, and they generate routed, DRC-aware candidates. They export back to formats like KiCad, Altium, or Cadence so you can finish and verify in your own tools.
Cost
Where errors get expensive
The cost of a mistake rises sharply with each stage you pass before catching it. Rename a mislabeled net during capture and the fix takes seconds. Catch that same error as a wrong connection after the board is fabricated and you are ordering a new batch.
| Caught at | What the fix is | Cost |
|---|---|---|
| Schematic: ERC | Edit a drawing, rename a net | Seconds |
| Board: DRC | Reroute copper before fab | Minutes to hours |
| After fabrication | Respin a physical board | Days + real money |
ERC, the electrical rule check, runs at the schematic level. It flags issues like an output pin driving another output, an unconnected input, or a power net with no source. Fixing an ERC violation means editing a drawing, which is cheap.
DRC runs at the board level and flags physical violations: traces too close together, a trace narrower than the fab allows, a via that collides with a pad. Fixing a DRC violation means rerouting copper, which is more work but still pre-fabrication.
Tooling
Mapping AI tools to stages
Once you see the three stages clearly, the tool landscape sorts itself out. Different tools reason about different problems: a schematic-capture model reasons about parts and connectivity, while a router reasons about geometry and physics under design rules.
| Tool | Stage it targets | What it actually does |
|---|---|---|
| ProtoFlow | Schematic capture | Plain-English prompt → editable, manufacturable schematic with real LCSC/DigiKey/Mouser parts, built-in DRC/ERC, one-click KiCad export. |
| Quilter | Layout + routing | Cloud AI that takes placed components plus an outline and produces routed results. |
| DeepPCB | Routing | Cloud AI router (InstaDeep) that routes an existing, placed board. |
| Flux | Schematic + layout | Browser-based ECAD environment with an AI copilot spanning both. |
| KiCad | All stages (manual) | Free, open-source desktop EDA backbone with no native AI of its own. |
Workflow
A practical 2026 workflow
A smart approach chains stage-specific tools rather than betting on a single do-everything product. One concrete path: use ProtoFlow for AI schematic capture, generating a verified schematic and netlist with real parts, then export the KiCad bundle. Move into KiCad for placement. Hand the placed board to an AI router such as Quilter or DeepPCB to draw copper. Finally, bring the routed board back and run human-supervised DRC and ERC before generating Gerbers.
# each handoff is a clean, swappable artifactcapture ProtoFlow → netlist + KiCad bundleplacement KiCad → placed .kicad_pcbrouting Quilter/DeepPCB → routed copperverify you + DRC/ERC → Gerbers✓ swap any one tool without disrupting the others
Each handoff is a clean artifact: a netlist out of capture, a placed .kicad_pcb out of layout, routed copper and then Gerbers out of routing. Because the boundaries are explicit, you can swap any one tool without disrupting the others. If a better AI router appears next year, you change one step.
Reference
Glossary
Netlist
A machine-readable list of every component, its assigned footprint, and which pins share an electrical net. The output of capture and the input to layout.
ERC: Electrical Rule Check
An automated check on the schematic that flags electrical mistakes such as conflicting outputs, unconnected pins, or unpowered nets.
DRC: Design Rule Check
An automated check on the board that flags physical violations such as insufficient trace spacing, undersized traces, or pad collisions, measured against your fabricator's rules.
Footprint
The physical land pattern, pads and dimensions, that a real component occupies on the board. Each schematic symbol must map to a correct footprint.
Gerber
The standard file format fabricators use to manufacture a board, describing each copper, mask, and silkscreen layer. Drill files accompany them for holes and vias.
Place-and-route
The combined layout-plus-routing stage: positioning footprints and then drawing the copper that connects them while honoring design rules.
Frequently asked questions
Is schematic capture the same as PCB layout?
No. Schematic capture defines components and their electrical connections as nets, producing a netlist. PCB layout takes that netlist and positions the physical footprints on a board. Capture is logical; layout is physical. They are separate stages with separate tools and separate failure modes.
Can one AI tool do schematic capture, layout, and routing?
Not reliably in 2026. These are genuinely different problems, so vendors specialize. ProtoFlow targets AI schematic capture; Quilter and DeepPCB target placement and routing on an existing board. Chaining stage-specific tools, with a human on final review, is more dependable than expecting one tool to excel at all three.
Does ProtoFlow route boards or do place-and-route?
No. ProtoFlow is scoped to schematic capture, which it calls step zero. It turns a plain-English prompt into an editable, manufacturable schematic with real LCSC, DigiKey, and Mouser parts, runs DRC/ERC, and exports a KiCad bundle. Placement and routing happen in tools like KiCad, Quilter, or DeepPCB.
What artifact does each EDA stage produce?
Schematic capture produces a netlist. Layout produces a board file, such as a KiCad project, with footprints positioned but copper not yet drawn. Routing produces Gerber and drill files, the format fabricators use to manufacture the board. Each artifact is the input to the next stage.
Why is it cheaper to fix errors during schematic capture?
Because a capture error is just an edit to a drawing, caught by ERC in seconds. The same mistake found after fabrication means rerouting or respinning a physical board, costing days and money. Correctness front-loaded into the schematic prevents expensive downstream surprises.
Sources
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