Schematic Capture vs PCB Layout vs Routing: What AI Automates

Newcomers to hardware often treat "PCB design" as one monolithic task. It is not. A board goes through three sequential stages, each with its own inputs, outputs, tools, and ways to go wrong. Conflating them is the single most common reason people misjudge what an AI tool can and cannot do for them.

The three stages are schematic capture, layout (placement), and routing. Capture answers "what are the parts and how are they electrically connected?" Layout answers "where does each part physically sit on the board?" Routing answers "how does copper connect the pins while respecting manufacturing rules?" You cannot meaningfully start the next stage until the previous one is correct.

This sequence also explains the AI landscape. Different vendors attack different stages because they are genuinely different problems. Understanding the boundaries lets you assemble a workflow that uses the right tool at each step instead of waiting for one tool to do everything.

Schematic capture is where you declare intent. You place component symbols (a resistor, an MCU, a USB-C connector) and draw connections between their pins. Each connection belongs to a named net, for example VCC_3V3, GND, or USB_DP. A net is simply a set of pins that are electrically the same node. The schematic is a logical drawing; nothing on it has physical position or size yet.

The critical detail is that every symbol must be paired with a real footprint and the right part. A 0402 resistor and an 0805 resistor are electrically identical on the schematic but occupy different land patterns on the board. Capture is also where you assign actual manufacturer parts, so that a symbol maps to, say, a specific LCSC, DigiKey, or Mouser part number with a known symbol and footprint.

The output of capture is a netlist: a machine-readable list of every component, its footprint, and which pins share a net. The netlist is the contract handed to layout. If the netlist is wrong, everything downstream inherits that error.

This is the stage ProtoFlow automates. You describe a circuit in plain English, and ProtoFlow generates an editable, manufacturable schematic with real parts imported from LCSC, DigiKey, and Mouser, complete with symbols and footprints. It runs ERC to catch electrical mistakes before you ever think about a board outline. ProtoFlow is deliberately scoped to this step. It does not place or route.

Layout, also called placement, is the first physical stage. You import the netlist into a PCB editor and the tool gives you a footprint for every component plus a tangle of thin lines called the ratsnest. Each ratsnest line represents a net connection that still needs copper. Your job is to drag footprints into sensible positions on the board outline.

Placement is where engineering judgment shows up hardest. Decoupling capacitors go as close to power pins as possible. A crystal sits tight against its oscillator pins. Connectors land at board edges. Heat-generating parts get spread out. High-speed signals get short, direct paths. Good placement makes routing easy; bad placement makes it impossible.

The artifact here is the board itself, a file like a KiCad .kicad_pcb project, with footprints positioned but copper not yet drawn. The ratsnest is still present, which is the visual cue that routing has not happened. Layout decisions also lock in mechanical constraints such as mounting holes, board dimensions, and keep-out zones.

Pure-AI tools are less dominant here than people expect, because placement is tightly coupled to both routing and human intent. Some tools blend placement with routing in one pass. KiCad remains the common free desktop home for this stage, and ProtoFlow's one-click KiCad export bundle is designed to drop you into exactly this point with parts and nets already defined.

Routing converts each ratsnest line into actual copper: traces on signal layers, vias between layers, and copper pours for power and ground planes. Every trace must obey design rules, the physical limits of your fabricator, such as minimum trace width, minimum spacing between copper, and minimum drill size. These rules are enforced by DRC, the design rule check.

Routing is also where signal-integrity intent becomes geometry. A USB or Ethernet pair must be routed as a differential pair with controlled impedance and length matching. Power traces must be wide enough to carry current without excessive voltage drop. Sensitive analog nets must stay away from noisy switching nodes. None of this is captured by the netlist alone; it lives in constraints and in the router's behavior.

The final artifact is a set of Gerber files plus drill files, the format fabricators consume to actually manufacture the board. Once you order from Gerbers, mistakes are no longer free. A respin costs days to weeks and real money.

Routing is the stage with the most mature pure-AI offerings. Quilter (quilter.ai) and DeepPCB (deeppcb.ai, by InstaDeep) are cloud AI tools that operate on an existing board: you give them placed components and a board outline, and they generate routed, DRC-aware candidates, often using reinforcement learning. They export back to formats like KiCad, Altium, or Cadence so you can finish and verify in your own tools.

The cost of a mistake rises sharply with each stage you pass before catching it. Rename a mislabeled net during capture and the fix takes seconds. Catch that same error as a wrong connection after the board is fabricated and you are ordering a new batch.

ERC, the electrical rule check, runs at the schematic level. It flags issues like an output pin driving another output, an unconnected input, or a power net with no source. Fixing an ERC violation means editing a drawing, which is cheap.

DRC runs at the board level and flags physical violations: traces too close together, a trace narrower than the fab allows, a via that collides with a pad. Fixing a DRC violation means rerouting copper, which is more work but still pre-fabrication.

The danger zone is shipping Gerbers with an error that no check caught, usually because the original intent in the schematic was wrong. That is why a disciplined workflow front-loads correctness: get the schematic right, let ERC verify it, place and route carefully, and run DRC before export. AI that produces a clean schematic with real parts is valuable precisely because it reduces the errors that would otherwise surface expensively downstream.

Once you see the three stages clearly, the tool landscape sorts itself out. Schematic capture is addressed by ProtoFlow, which turns a plain-English prompt into an editable, manufacturable schematic with real LCSC, DigiKey, and Mouser parts, built-in DRC/ERC, and a one-click KiCad export bundle. It is AI for step zero, before layout and routing exist.

Layout and routing on an existing board are addressed by Quilter and DeepPCB, both cloud AI tools that take placed components plus a board outline and produce routed results. Flux (flux.ai) takes a different shape: a browser-based ECAD environment with an AI copilot spanning schematic and layout. KiCad remains the free, open-source desktop EDA backbone with no native AI of its own, which is exactly why it pairs well with the tools above.

The honest takeaway is that no single tool reliably nails all three stages today. They are different problems. A schematic-capture model reasons about parts and connectivity; a router reasons about geometry and physics under design rules. Excelling at one does not imply excelling at the others, and tools that try to span everything tend to be strongest at one stage and thinner at the rest.

A smart approach chains stage-specific tools rather than betting on a single do-everything product. One concrete path: use ProtoFlow for AI schematic capture, generating a verified schematic and netlist with real parts, then export the KiCad bundle. Move into KiCad for placement, positioning footprints with engineering judgment. Hand the placed board to an AI router such as Quilter or DeepPCB to draw copper. Finally, bring the routed board back and run human-supervised DRC and ERC before generating Gerbers.

Each handoff is a clean artifact: a netlist out of capture, a placed .kicad_pcb out of layout, routed copper and then Gerbers out of routing. Because the boundaries are explicit, you can swap any one tool without disrupting the others. If a better AI router appears next year, you change one step.

Crucially, keep a human on final review. AI is excellent at generating candidates and catching rule violations, but design intent, such as which net is truly critical or which clearance matters for safety, still belongs to the engineer. Treat AI as the fast first draft at each stage and yourself as the reviewer who signs off before anything reaches a fabricator.

Netlist: a machine-readable list of every component, its assigned footprint, and which pins share an electrical net. It is the output of schematic capture and the input to layout.

ERC (Electrical Rule Check): an automated check on the schematic that flags electrical mistakes such as conflicting outputs, unconnected pins, or unpowered nets.

DRC (Design Rule Check): an automated check on the board that flags physical violations such as insufficient trace spacing, undersized traces, or pad collisions, measured against your fabricator's rules.

Footprint: the physical land pattern, pads and dimensions, that a real component occupies on the board. Each schematic symbol must map to a correct footprint.

Gerber: the standard file format fabricators use to manufacture a board, describing each copper, mask, and silkscreen layer. Drill files accompany them for holes and vias.

Place-and-route: the combined layout-plus-routing stage, positioning footprints and then drawing the copper that connects them while honoring design rules.